49 lines
1.7 KiB
Diff
49 lines
1.7 KiB
Diff
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From 3738b1f05101506d8221d1d0baffe93f1bfc2a91 Mon Sep 17 00:00:00 2001
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From: Coelacanthus <coelacanthus@outlook.com>
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Date: Mon, 23 May 2022 15:35:00 +0800
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Subject: [PATCH] riscv: fix compitible with binutils 2.38
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commit 6df2a016c0c8a3d0933ef33dd192ea6606b115e3 from linux kernel
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Since binutils 2.38, default ISA spec version switch to 20191213,
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in this version, original I extension be split into I, Zicsr and Zifencei.
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Zicsr is csr read/write (csrr*/csrw*) instructions, and Zifencei
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is fence.i instruction.
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This will cause compile error like this:
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Error: unrecognized opcode `csrr a5,0xc01'
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Error: unrecognized opcode `fence.i'
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This commit add code to detect new Zicsr and Zifencei extensions,
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and enable it when needed.
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Signed-off-by: Coelacanthus <coelacanthus@outlook.com>
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Cc: Rick Chen <rick@andestech.com>
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Cc: Leo <ycliang@andestech.com>
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---
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arch/riscv/Makefile | 9 ++++++++-
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1 file changed, 8 insertions(+), 1 deletion(-)
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diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
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index 0b80eb8d86..62712f8d38 100644
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--- a/arch/riscv/Makefile
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+++ b/arch/riscv/Makefile
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@@ -24,7 +24,14 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
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CMODEL = medany
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endif
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-ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \
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+RISCV_MARCH_y = $(ARCH_BASE)$(ARCH_A)$(ARCH_C)
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+
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+# Newer binutils versions default to ISA spec version 20191213 which moves some
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+# instructions from the I extension to the Zicsr and Zifencei extensions.
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+toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH_y)_zicsr_zifencei)
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+RISCV_MARCH_$(toolchain-need-zicsr-zifencei) := $(RISCV_MARCH_y)_zicsr_zifencei
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+
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+ARCH_FLAGS = -march=$(RISCV_MARCH_y) -mabi=$(ABI) \
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-mcmodel=$(CMODEL)
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PLATFORM_CPPFLAGS += $(ARCH_FLAGS)
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--
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2.36.1
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