maintain: update u-boot to v2022.10 & opensbi to v1.1
Signed-off-by: Celeste Liu <CoelacanthusHex@gmail.com>
This commit is contained in:
parent
5d7dbdbe37
commit
50cc973369
3 changed files with 4 additions and 170 deletions
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@ -1,48 +0,0 @@
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From 3738b1f05101506d8221d1d0baffe93f1bfc2a91 Mon Sep 17 00:00:00 2001
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From: Coelacanthus <coelacanthus@outlook.com>
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Date: Mon, 23 May 2022 15:35:00 +0800
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Subject: [PATCH] riscv: fix compitible with binutils 2.38
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commit 6df2a016c0c8a3d0933ef33dd192ea6606b115e3 from linux kernel
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Since binutils 2.38, default ISA spec version switch to 20191213,
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in this version, original I extension be split into I, Zicsr and Zifencei.
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Zicsr is csr read/write (csrr*/csrw*) instructions, and Zifencei
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is fence.i instruction.
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This will cause compile error like this:
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Error: unrecognized opcode `csrr a5,0xc01'
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Error: unrecognized opcode `fence.i'
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This commit add code to detect new Zicsr and Zifencei extensions,
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and enable it when needed.
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Signed-off-by: Coelacanthus <coelacanthus@outlook.com>
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Cc: Rick Chen <rick@andestech.com>
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Cc: Leo <ycliang@andestech.com>
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---
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arch/riscv/Makefile | 9 ++++++++-
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1 file changed, 8 insertions(+), 1 deletion(-)
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diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
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index 0b80eb8d86..62712f8d38 100644
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--- a/arch/riscv/Makefile
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+++ b/arch/riscv/Makefile
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@@ -24,7 +24,14 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
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CMODEL = medany
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endif
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-ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \
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+RISCV_MARCH_y = $(ARCH_BASE)$(ARCH_A)$(ARCH_C)
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+
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+# Newer binutils versions default to ISA spec version 20191213 which moves some
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+# instructions from the I extension to the Zicsr and Zifencei extensions.
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+toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH_y)_zicsr_zifencei)
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+RISCV_MARCH_$(toolchain-need-zicsr-zifencei) := $(RISCV_MARCH_y)_zicsr_zifencei
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+
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+ARCH_FLAGS = -march=$(RISCV_MARCH_y) -mabi=$(ABI) \
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-mcmodel=$(CMODEL)
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PLATFORM_CPPFLAGS += $(ARCH_FLAGS)
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--
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2.36.1
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To: u-boot@lists.denx.de
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Cc: Xiang W <wxjstz@126.com>,
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Felix Yan <felixonmars@archlinux.org>
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Subject: [PATCH] virtio: pci: fix bug of virtio_pci_map_capability
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Date: Mon, 29 Aug 2022 07:53:15 +0800
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The bar of the structure virtio_pci_cap is the index, and each base
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address occupies 4 bytes, so it needs to be multiplied by 4.
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This patch fixes a bug reported by Felix Yan
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https://lists.denx.de/pipermail/u-boot/2022-August/492779.html
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Signed-off-by: Xiang W <wxjstz@126.com>
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Tested-by: Felix Yan <felixonmars@archlinux.org>
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---
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drivers/virtio/virtio_pci_modern.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/drivers/virtio/virtio_pci_modern.c b/drivers/virtio/virtio_pci_modern.c
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index 880a12cc28..cfde4007f5 100644
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--- a/drivers/virtio/virtio_pci_modern.c
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+++ b/drivers/virtio/virtio_pci_modern.c
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@@ -466,7 +466,7 @@ static void __iomem *virtio_pci_map_capability(struct udevice *udev,
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unsigned long mask =
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PCI_REGION_TYPE | PCI_REGION_SYS_MEMORY | PCI_REGION_RO;
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unsigned long flags = PCI_REGION_MEM;
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- u8 *p = dm_pci_map_bar(udev, PCI_BASE_ADDRESS_0 + cap->bar, cap->offset,
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+ u8 *p = dm_pci_map_bar(udev, PCI_BASE_ADDRESS_0 + 4 * cap->bar, cap->offset,
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cap->length, mask, flags);
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return (void __iomem *)p;
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11
mkimg
11
mkimg
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@ -85,11 +85,10 @@ pushd u-boot
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git checkout master
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git checkout master -- ':(top)'
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git pull --rebase
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git checkout v2022.07
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git checkout v2022.10
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msg2 "Apply binutils 2.38 compitible patch"
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git apply ../0001-riscv-fix-compitible-with-binutils-2.38.patch
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msg2 "Apply 'virtio: pci: fix bug of virtio_pci_map_capability' patch"
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git apply ../0002-virtio-pci-fix-bug-of-virtio_pci_map_capability.patch
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git cherry-pick -n 1dde977518f13824b847e23275001191139bc384
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make \
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CROSS_COMPILE=riscv64-linux-gnu- \
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qemu-riscv64_smode_defconfig
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git checkout master
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git checkout master -- ':(top)'
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git pull --rebase
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git checkout v1.0
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msg2 "Apply binutils 2.38 compitible patch"
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git cherry-pick -n 5d53b55aa77ffeefd4012445dfa6ad3535e1ff2c
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git checkout v1.1
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make \
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CROSS_COMPILE=riscv64-linux-gnu- \
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